1. Field of the Invention
The present invention relates to a method and apparatus for detecting faults in memory elements, and more particularly relates to detecting faults using built-in self-test (BIST).
2. Description of the Prior Art
During the production of integrated circuits, silicon wafers are manufactured which typically have a large number of die. Each die may contain a circuit, such as an application specific integrated circuit (ASIC). Once the wafers have completed processing, wafer level testing is performed to determine whether the die are functional and/or meet another desired specifications. Typically a large portion of the die on a wafer must be discarded due to manufacturing defects.
Some defects may cause a die to be non-functional. For example, a dust particle that is present during a masking operation may result in one or more logic elements being nonfunctional. Other defects may cause a die to not meet other specifications, such as operating speed. In either case, die that have even a single defect are often deemed unusable, and discarded. The number of usable die divided by the number of total tested die is defined as die yield. Typically, 20 to 30 percent of the die on a wafer must be usable for the production of an ASIC design to be commercially feasible.
Modern integrated circuits are increasing in both density and size. Both of these factors tend to decrease the die yield. As the die area increases, there is an increased probability that a defect will occur on the die. Likewise, as the density increases, the manufacturing tolerances are typically reduced and the chance for a defect is also increased.
Die containing a large number of storage devices, such as random access memories (RAM) or read only memories (ROM), are particularly susceptible to processing defects. RAMs and ROMs are typically designed using minimum width and spacings dimensions to achieve the largest number of storage elements in the smallest possible area. RAMs and ROMs are typically the most dense circuit elements of a circuit design, and can consume a substantial portion of the die area.
The memory elements in an ASIC design are often not directly accessible from the chip I/O pins. To detect these types of defects, techniques such as built-in self-test (BIST) have been developed. BIST circuitry is typically designed directly into the circuit design, and often includes providing a number of serial scan chains within the circuit design. Serial scan test vectors may then be shifted through the serial scan chains to control selected nodes therein. The circuit design may then be clocked once by the functional clock, and the results may be serially shifted out of the serial scan chains and compared to an expected value. Using BIST in this manner is well known in the art, and can improve the fault coverage that can be obtained for a given circuit design.
The standard method for testing a circuit design, using BIST or otherwise, is to test a particular die until a single defect is detected. After a single defect is detected, the test is typically terminated and the die is marked as unusable or discarded. Because modern integrated circuits have an increased probability of having a defect therein, as described above, discarding a die because of a single defect can reduced the commercially feasible of producing many ASIC designs. This is particularly true for those ASIC designs that include large or many memory elements.